Exemplary embodiments relate to a method of operating a nonvolatile memory device and, more particularly, to a method of programming a nonvolatile memory device, which can reduce the time taken to perform a verification operation.
Program, erase, read, and verification operations are performed on a nonvolatile memory device.
While the program or erase operation is performed, the verification operation is performed. In particular, as the number of bits of data that are programmed is increased, the time that it takes to perform the verification operation for the program operation increases. The verification operation is described in detail below.
FIG. 1 is a diagram illustrating a nonvolatile memory device.
The nonvolatile memory device includes a memory cell array 10 for storing data, a bit line control circuit 20 for selecting a bit line BLe or BLo, and a page buffer 30 for controlling input and output operations of the data.
The memory cell array 10 includes a plurality of strings Ste and Sto, each including a drain select transistor DST and a source select transistor SST. Each of the strings further includes a plurality of memory cells F0 to Fn coupled in series between the drain select transistor DST and the source select transistor SST. The drains of the drain select transistors DST of the strings are coupled to the bit lines BLe and BLo, respectively, and the sources of the source select transistors SST of the strings are coupled to a common source line CSL in common.
The gates of the drain select transistors DST of the strings are interconnected to a drain select line DSL, and the gates of the source select transistors SST of the strings are interconnected to a source select line SSL. Furthermore, the gates of the memory cells, which are arranged in a row across the strings, i.e., the memory cells Fn, are interconnected to a corresponding word line, i.e., WLn.
The bit line control circuit 20 includes an even switching element 21 and an odd switching element 22. The even switching element 21 is operated in response to an even sense pulse BSLe and configured to select the even bit line BLe. The odd switching element 22 is operated in response to an odd sense pulse BSLo and configured to select the odd bit line BLo.
The page buffer 30 is coupled to a selected one of the bit lines BLe and BLo through the bit line control circuit 20 and configured to verify whether a selected memory cell has been programmed in a verification operation.
FIG. 2 is a diagram illustrating a conventional method of programming a nonvolatile memory device.
An operation of programming the nonvolatile memory device in the case in which the even bit line BLe is selected is described below with reference to FIGS. 1 and 2.
When a program operation is performed, the page buffer 30 precharges or discharges a sense node SO on the basis of data inputted to the page buffer 30. It is preferred that the sense node SO coupled to the string of a cell to be programmed be discharged. When the even switching element 21 is supplied with the even sense pulse BSLe of a logic high level and turned on, the even bit line BLe is discharged to a ground voltage (0 V) level. Here, when a program voltage is supplied to a selected word line Sel. WL, selected memory cells are programmed. A pass voltage is supplied to the remaining word lines other than the selected word line Sel. WL. Through the above-described program operation, each of the threshold voltages of the selected memory cells may rise up to a first target level, a second target level, or a third target level. When the even sense pulse BSLe and the program voltage supplied to the selected word line Sel. WL shift to a logic low level, the program operation is stopped and a verification operation is then performed.
The verification operation is performed to verify whether each of the threshold voltages of the selected memory cells has reached a selected one of the first to third target voltages. Accordingly, the verification operation is performed by supplying different levels of verification voltages according to the respective target levels. More particularly, the memory cell can be in an erase state in which the threshold voltage is lower than 0 V or can be in a program state in which the threshold voltage is higher than 0 V (i.e., a first state PV1, a second state PV2, and a third state PV3 in order of higher threshold voltages). Accordingly, in the verification operation, a first verification operation, a second verification operation, and a third verification operation may be performed.
In order to perform the verification operation, the sense node SO is precharged to a high voltage level.
In the first verification operation, a first verification voltage Vr1 is supplied to the selected word line Sel. WL. The even switching element 21 is turned on in response to the even sense pulse BSLe having a first sense pulse (V1) level. Here, the first sense pulse V1 is a signal for a bit line precharge pulse. The precharged sense node SO and the even bit line BLe are coupled together, and then the even bit line BLe is also precharged to a high voltage level on the basis of a potential of the precharged sense node SO. More particularly, the even bit line BLe is precharged to a voltage (V1-Vt) level. Here, a voltage Vt is the threshold voltage of the even switching element 21.
When the even bit line BLe is precharged and the even sense pulse BSLe becomes a low logic level, the even switching element 21 is turned off. During the time for which the even switching element 21 is turned off, the even bit line BLe can have a different voltage level (A or B) according to threshold voltage levels of the selected memory cells. For example, if the selected memory cells have threshold voltages lower than a first target level in the first verification operation, a channel is formed on the selected memory cells and so the voltage level of the even bit line BLe is lowered by a grounded common source line CSL (B). Meanwhile, if the selected memory cells have threshold voltages higher than the first target level, a channel is not formed on the selected memory cells and so the voltage level of the even bit line BLe remains intact (A). And then, the even sense pulse BSLe becomes a second sense pulse (V2) level, and the page buffer 30 senses a shift in the voltage level of the even bit line BLe in the second verification operation.
Meanwhile, in each of the second verification operation and the third verification operation, the sense operation is performed after a corresponding bit line is precharged. Accordingly, the time that it takes to perform the verification operation may be increased.